/*
 * COPYRIGHT (c) 2017-2021 Gigadevice Semiconductor(Beijing) INC.
 * SPI Flash Low Level Driver (LLD) Sample Code
 *
 * SPI interface command hex code, type definition and function prototype.
 *
 * $Id: GD25Q128E_CMD.h,v 1.3 2021/07/15 16:44:11 mxclldb1 Exp $
 */
#ifndef    __GD25Q128E_CMD_H__
#define    __GD25Q128E_CMD_H__
#include "stdint.h"
#include    "GD25Q128E_DEF.h"
#include <stdint.h>
#include "app_spi.h"
#include "app_spi_dma.h"


#define FLASH_CS_PIN                     APP_IO_PIN_10
#define FLASH_CLK_PIN                    APP_IO_PIN_15
#define FLASH_MOSI_PIN                   APP_IO_PIN_14
#define FLASH_MISO_PIN                   APP_IO_PIN_13
#define FLASH_CS_IO_TYPE                 APP_IO_TYPE_GPIOA
#define FLASH_CLK_IO_TYPE                APP_IO_TYPE_GPIOA
#define FLASH_MOSI_IO_TYPE               APP_IO_TYPE_GPIOA
#define FLASH_MISO_IO_TYPE               APP_IO_TYPE_GPIOA
#define FLASH_CS_PINMUX                  APP_IO_MUX_2
#define FLASH_CLK_PINMUX                 APP_IO_MUX_2
#define FLASH_MOSI_PINMUX                APP_IO_MUX_2
#define FLASH_MISO_PINMUX                APP_IO_MUX_2
/*** MX25 series command hex code definition ***/

#define SPI_FLASH_CMD_WRSR              0x01
#define SPI_FLASH_CMD_WRSR1             0x31
#define SPI_FLASH_CMD_RDSR              0x05

#define SPI_FLASH_CMD_WREN              0x06
#define SPI_FLASH_CMD_WRDI              0x04

#define SPI_FLASH_CMD_READ              0x03
#define SPI_FLASH_CMD_FREAD             0x0B
#define SPI_FLASH_CMD_DOFR              0x3B
#define SPI_FLASH_CMD_DIOFR             0xBB
#define SPI_FLASH_CMD_QOFR              0x6B
#define SPI_FLASH_CMD_QIOFR             0xEB
#define SPI_FLASH_CMD_READ_RESET        0xFF

#define SPI_FLASH_CMD_PP                0x02
#define SPI_FLASH_CMD_QPP               0x32
#define SPI_FLASH_CMD_SE                0x20
#define SPI_FLASH_CMD_BE_32             0x52
#define SPI_FLASH_CMD_BE_64             0xD8
#define SPI_FLASH_CMD_CE                0xC7
#define SPI_FLASH_CMD_PES               0x75
#define SPI_FLASH_CMD_PER               0x7A

#define SPI_FLASH_CMD_RDI               0xAB
#define SPI_FLASH_CMD_REMS              0x90
#define SPI_FLASH_CMD_RDID              0x9F

#define SPI_FLASH_CMD_RSTEN             0x66
#define SPI_FLASH_CMD_RST               0x99
#define SPI_FLASH_CMD_DP                0xB9
#define SPI_FLASH_CMD_RDP               0xAB
#define DUMMY_BYTE                      0xFF
void spi_flash_init_1(uint32_t clock_prescaler);
uint32_t spi_flash_read_id(void);
void spi_flash_sector_erase(uint32_t dst);
void spi_flash_chip_erase(void);
void spi_flash_page_program(uint32_t dst, uint8_t *data, uint32_t nbytes);
void spi_flash_read_1(uint32_t dst, uint8_t *buffer, uint32_t nbytes);
void spi_flash_fast_read(uint32_t dst, uint8_t *buffer, uint32_t nbytes);
void spi_flash_reset(void);
void spi_flash_power_down(void);
void spi_flash_wakeup(void);
void read_res(uint8_t res_index);
//ID comands
#define    FLASH_CMD_RDID      0x9F    //RDID (Read Identification)
#define    FLASH_CMD_RES       0xAB    //RES (Read Electronic ID)
#define    FLASH_CMD_REMS      0x90    //REMS (Read Electronic & Device ID)
#define    FLASH_CMD_QPIID     0xAF    //QPIID (QPI ID Read)

//Register comands
#define    FLASH_CMD_WRSR      0x01    //WRSR (Write Status Register)
#define    FLASH_CMD_RDSR      0x05    //RDSR (Read Status Register)
#define    FLASH_CMD_RDSR2     0x35    //RDSR2 (Read Configuration Register)


//READ comands
#define    FLASH_CMD_READ        0x03    //READ (1 x I/O)
#define    FLASH_CMD_2READ       0xBB    //2READ (2 x I/O)
#define    FLASH_CMD_4READ       0xEB    //4READ (4 x I/O)
#define    FLASH_CMD_FASTREAD    0x0B    //FAST READ (Fast read data).
#define    FLASH_CMD_DREAD       0x3B    //DREAD (1In/2 Out fast read)
#define    FLASH_CMD_QREAD       0x6B    //QREAD (1In/4 Out fast read)
#define    FLASH_CMD_4DTRD       0xED    //4DTRD (Quad DT read)
#define    FLASH_CMD_RDSFDP      0x5A    //RDSFDP (Read SFDP)

//Program comands
#define    FLASH_CMD_WREN     0x06    //WREN (Write Enable)
#define    FLASH_CMD_WRDI     0x04    //WRDI (Write Disable)
#define    FLASH_CMD_PP       0x02    //PP (page program)
#define    FLASH_CMD_4PP      0x38    //4PP (Quad page program)

//Erase comands
#define    FLASH_CMD_SE       0x20    //SE (Sector Erase)
#define    FLASH_CMD_BE32K    0x52    //BE32K (Block Erase 32kb)
#define    FLASH_CMD_BE       0xD8    //BE (Block Erase)
#define    FLASH_CMD_CE       0x60    //CE (Chip Erase) hex code: 60 or C7

//Mode setting comands
#define    FLASH_CMD_DP       0xB9    //DP (Deep Power Down)
#define    FLASH_CMD_RDP      0xAB    //RDP (Release form Deep Power Down)
#define    FLASH_CMD_EQIO     0x35    //EQIO (Enable Quad I/O)

//Reset comands
#define    FLASH_CMD_RSTEN     0x66    //RSTEN (Reset Enable)
#define    FLASH_CMD_RST       0x99    //RST (Reset Memory)
#define    FLASH_CMD_RSTQIO    0xFF    //RSTQIO (Reset Quad I/O)


//Suspend/Resume comands
#define    FLASH_CMD_PGM_ERS_S    0x75    //PGM/ERS Suspend (Suspends Program/Erase) old: 0xB0
#define    FLASH_CMD_PGM_ERS_R    0x7A    //PGM/ERS Erase (Resumes Program/Erase) old: 0x30

// Return Message
typedef enum {
    FlashOperationSuccess,
    FlashWriteRegFailed,
    FlashTimeOut,
    FlashIsBusy,
    FlashCmdSpiOnly,
    FlashCmdQpiOnly,
    FlashQuadNotEnable,
    FlashAddressInvalid,
    FlashCmd3ByteOnly
}ReturnMsg;

// Flash status structure define
struct sFlashStatus{
    /* Mode Register:
     * Bit  Description
     * -------------------------
     *  7   RYBY enable
     *  6   Reserved
     *  5   Reserved
     *  4   Reserved
     *  3   Reserved
     *  2   Reserved
     *  1   Parallel mode enable
     *  0   QPI mode enable
    */
    uint8    ModeReg;
    BOOL     ArrangeOpt;
};

typedef struct sFlashStatus FlashStatus;

/* Basic functions */
void spi_flash_init(uint32_t clock_prescaler);
void CS_High(void);
void CS_Low(void);
void InsertDummyCycle( uint8 dummy_cycle);
void SendByte( uint8 byte_value, uint8 transfer_type );
uint8 GetByte( uint8 transfer_type );

/* Utility functions */
void Wait_Flash_WarmUp(void);
void Initial_Spi(void);
BOOL WaitFlashReady( uint32  ExpectTime, FlashStatus *fsptr );
BOOL WaitRYBYReady( uint32 ExpectTime );
BOOL IsFlashBusy( FlashStatus *fsptr );
BOOL IsFlashQPI( FlashStatus *fsptr );
BOOL IsFlashQIO( FlashStatus *fsptr );
BOOL IsFlash4Byte( FlashStatus *fsptr );
void SendFlashAddr( uint32 flash_address, uint8 io_mode, BOOL addr_4byte_mode );
uint8 GetDummyCycle(uint32 default_cycle, FlashStatus *fsptr );

/* Flash commands */
ReturnMsg CMD_RDID( uint32 *Identification, FlashStatus *fsptr );

ReturnMsg CMD_REMS( uint16 *REMS_Identification, FlashStatus *fsptr );
ReturnMsg CMD_QPIID( uint32 *Identification, FlashStatus *fsptr );

ReturnMsg CMD_RDSR( uint8 *StatusReg, FlashStatus *fsptr );
#ifdef SUPPORT_WRSR2
   ReturnMsg CMD_WRSR( uint16 UpdateValue, FlashStatus *fsptr );
#else
   ReturnMsg CMD_WRSR( uint8 UpdateValue, FlashStatus *fsptr );
#endif
ReturnMsg CMD_RDSR2( uint8 *ConfigReg, FlashStatus *fsptr );

ReturnMsg CMD_READ( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_2READ( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_4READ( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_DREAD( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_QREAD( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_FASTREAD( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_RDSFDP( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );

ReturnMsg CMD_4DTRD( uint32 flash_address, uint8 *target_address, uint32 byte_length, FlashStatus *fsptr );


ReturnMsg CMD_WREN( FlashStatus *fsptr );
ReturnMsg CMD_WRDI( FlashStatus *fsptr );
ReturnMsg CMD_PP( uint32 flash_address, uint8 *source_address, uint32 byte_length, FlashStatus *fsptr );
ReturnMsg CMD_4PP( uint32 flash_address, uint8 *source_address, uint32 byte_length, FlashStatus *fsptr );

ReturnMsg CMD_SE( uint32 flash_address, FlashStatus *fsptr );
ReturnMsg CMD_BE32K( uint32 flash_address, FlashStatus *fsptr );
ReturnMsg CMD_BE( uint32 flash_address, FlashStatus *fsptr );
ReturnMsg CMD_CE( FlashStatus *fsptr );
ReturnMsg CMD_DP( FlashStatus *fsptr );
ReturnMsg CMD_RDP( FlashStatus *fsptr );
ReturnMsg CMD_EQIO( FlashStatus *fsptr );

ReturnMsg CMD_RSTEN( FlashStatus *fsptr );
ReturnMsg CMD_RST( FlashStatus *fsptr );
ReturnMsg CMD_RSTQIO( FlashStatus *fsptr );

ReturnMsg CMD_PGM_ERS_S( FlashStatus *fsptr );
ReturnMsg CMD_PGM_ERS_R( FlashStatus *fsptr );

void SwitchBank( BOOL bank);
uint8 FlashID_Test( uint8 QPI_Enable );
uint8 FlashReadWrite_Test( uint8 QPI_Enable );
void flash_write(uint32_t flash_addr,uint32_t trans_len,uint8_t *memory_addr);
void flash_read(uint32_t flash_addr,uint32_t trans_len,uint8_t *memory_addr);
void flash_erase(uint32_t flash_addr);
 void spi_flash_sector_erase_1(uint32_t dst);
 void spi_flash_page_program_1(uint32_t dst, uint8_t *data, uint32_t nbytes);
extern BOOL  flash_bank_flag ;
void write_picToflash(void);
#define ADDR_LOGO   0
//#define ADDR_HEALTH  (4*4096)
#define ADDR_TEMP    (10*4096)
#define ADDR_SLEEP    (16*4096)
#define ADDR_HISTORY  (22*4096)
#define ADDR_SET      (34*4096)
#define ADDR_SPORT    (28*4096)
#define LENTH_P        (20000)

#endif    /* __GD25Q128E_H__ */
